Nonvolatile semiconductor memory and method of fabrication thereof

ABSTRACT

A method of fabricating a semiconductor memory having word lines and bit lines disposed on a semiconductor substrate, with memory cells being formed at intersecting portions of the word lines and the bit lines. The method includes forming a first insulating film on the semiconductor substrate, forming a first polysilicon film on the first insulating film, patterning the first polysilicon film to form floating gates of the memory cells and an etching stop layer covering and surrounding contact portions of the word lines in a plan view, forming a second insulating film on the first polysilicon film, forming a conductive film on the second insulating film, patterning the conductive film to form control gates of the memory cells and strip-shaped regions as the word lines, accumulating an interlayer insulating film on the conductive film, and etching the interlayer insulating film, and opening contact holes for the contact portions.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a division of U.S. patent application Ser. No.11/878,850, filed on Jul. 27, 2007, which is based on, and claimspriority to, Japanese Patent Application No. 2006-230018, contents ofwhich are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a nonvolatile semiconductor memoryhaving a stacked gate structure including a floating gate, and to amethod of fabrication thereof, and in particular, the present inventionrelates to an improved technique for reducing poor fabrication of such anonvolatile semiconductor memory.

2. Description of the Related Art

A conventional nonvolatile semiconductor memory such as an EEPROM or thelike (see, for example, Japanese Patent Application Laid-Open (JP-A) No.7-249746) has a memory array in which the word lines and bit linesintersect in a plane, and transistors having stacked gate structures,which are formed from a floating gate and a control gate, are formed atthese intersecting portions.

In such a nonvolatile semiconductor memory, the control gate is formedof an electrically conductive film of polysilicon or the like. In orderto make this polysilicon be conductive with the circuits at theperiphery of the memory array (the peripheral circuits) and form theword lines, usually, contacts must be opened, and the polysilicon andthe metal wires (e.g., aluminum wires) at the peripheral circuits mustbe connected via these contacts.

However, in recent years, accompanying the advance of microfabricationtechnology in semiconductor memories, the intervals between adjacentword lines (the polysilicon) have become narrower. For this reason, atthe time of opening the aforementioned contacts, it has become difficultto open the contacts with precision above the polysilicon where thecontrol gates are formed. If the contacts cannot be opened withprecision above the polysilicon, there is the concern that problems willarise, such as the metal wires at the peripheral circuits will beconductive with the substrate of the nonvolatile semiconductor memory,or the like. Namely, in the process of opening the contacts,over-etching is carried out in order to avoid poor opening. However,there is the concern that, due to this over-etching, the field oxidefilm will be etched and the contacts will reach to the substrate. If thecontacts reach to the substrate, the problem arises that the electricsignals from the peripheral circuits cannot be transferred to thecontrol gates via the word lines.

On the other hand, due to the capabilities of the fabricating devicesand the like, there are limits on precisely opening contacts above thepolysilicon regardless of the intervals between the adjacent word lines(the polysilicon).

From the above, there have been desired a nonvolatile semiconductormemory of a structure in which electric signals from peripheral circuitsare reliably transferred to control gates via word lines even if contactholes cannot be precisely opened above the word lines, and a method offabricating such a nonvolatile semiconductor memory.

SUMMARY OF THE INVENTION

The invention provides a nonvolatile semiconductor memory in which aplurality of word lines and a plurality of bit lines are disposed on asemiconductor substrate, and which has memory cells at intersectingportions of the word lines and the bit lines, the nonvolatilesemiconductor memory having: a first insulating film formed on thesemiconductor substrate; an etching stop layer of a first shape which isformed on the first insulating film and which, in plan view, includes atleast contact portions of the word lines and metal wires of an upperlayer; a second insulating film formed on the etching stop layer; and aconductive film and formed on the second insulating film as the wordlines.

In accordance with the nonvolatile semiconductor memory of theinvention, in an etching process at the time of opening contact holes atcontact portions of word lines (the conductive film) and metal wires ofan upper layer, even in cases in which the contact holes cannot beprecisely opened above the conductive film, the etching stop layer whichis beneath the conductive film is formed in shapes (the first shapes)which include the contact portions, and therefore, the etching isstopped at this etching stop layer. Accordingly, the semiconductorsubstrate is not damaged, and poor junctions do not arise.

A method of fabricating a nonvolatile semiconductor memory of theinvention is a method of fabricating a nonvolatile semiconductor memoryin which a plurality of word lines and a plurality of bit lines aredisposed on a semiconductor substrate, and which has memory cells atintersecting portions of the word lines and the bit lines, the methodincluding: forming a first insulating film on the semiconductorsubstrate; forming a first polysilicon film on the first insulatingfilm; patterning the first polysilicon film, and forming floating gatesof the memory cells, and forming first shapes which include contactportions of the word lines and metal wires of an upper layer; forming asecond insulating film on the first polysilicon film; forming aconductive film on the second insulating film; patterning the conductivefilm, and forming control gates of the memory cells, and formingstrip-shaped regions as the word lines; accumulating an interlayerinsulating film on the conductive film; and etching the interlayerinsulating film, and opening, above the conductive film, contact holesfor the contact portions.

In accordance with the method of fabricating a nonvolatile semiconductormemory of the invention, before carrying out a process (contact holeetching process) in which the interlayer insulating film is etched andcontact holes for contact portions are formed above the conductive film,the first polysilicon film is already formed in shapes (the firstshapes) which include the contact portions. Then, in the contact holeetching step, even in cases in which the contact holes cannot be openedwith precision above the conductive film, the first polysilicon film ofthe first shape, which is formed beneath the conductive film, functionsas an etching stop layer. Accordingly, in a nonvolatile semiconductormemory which is fabricated in accordance with this fabricating method,the semiconductor substrate is not damaged by the contact hole etchingprocessing, and poor junctions do not arise.

Further, in this fabricating method, the floating gates of the memorycells, and the first shapes which include the contact portions of theword lines and the metal wires of the upper layer, are formedsimultaneously by patterning the first polysilicon film. Accordingly, anadditional process for forming the first polysilicon film as the etchingstop layer is not needed.

In accordance with the present invention, even if contact holes cannotbe opened accurately above word lines, electric signals from peripheralcircuits can be reliably transferred to control gates via the wordlines.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred exemplary embodiments of the present invention will bedescribed in detail based on the following figures wherein:

FIG. 1 is a plan view showing a portion of a memory cell array of anEEPROM relating to an exemplary embodiment;

FIG. 2A is a cross-sectional view showing a method of fabricating anEEPROM relating to the exemplary embodiment;

FIG. 2B is a cross-sectional view showing the method of fabricating theEEPROM relating to the exemplary embodiment;

FIG. 2C is a cross-sectional view showing the method of fabricating theEEPROM relating to the exemplary embodiment;

FIG. 3A is a cross-sectional view showing the method of fabricating theEEPROM relating to the exemplary embodiment;

FIG. 3B is a cross-sectional view showing the method of fabricating theEEPROM relating to the exemplary embodiment;

FIG. 3C is a cross-sectional view showing the method of fabricating theEEPROM relating to the exemplary embodiment;

FIG. 4A is a cross-sectional view showing the method of fabricating theEEPROM relating to the exemplary embodiment;

FIG. 4B is a cross-sectional view showing the method of fabricating theEEPROM relating to the exemplary embodiment;

FIG. 4C is a cross-sectional view showing the method of fabricating theEEPROM relating to the exemplary embodiment;

FIG. 5A is a cross-sectional view showing the method of fabricating theEEPROM relating to the exemplary embodiment;

FIG. 5B is a cross-sectional view showing the method of fabricating theEEPROM relating to the exemplary embodiment, and is a cross-sectionalview along segment B-B of FIG. 1;

FIG. 5C is a cross-sectional view showing the method of fabricating theEEPROM relating to the exemplary embodiment, and is a cross-sectionalview along segment C-C of FIG. 1;

FIG. 6A is a cross-sectional view showing the method of fabricating theEEPROM relating to the exemplary embodiment, and is a cross-sectionalview along segment A-A of FIG. 1;

FIG. 6B is a cross-sectional view showing the method of fabricating theEEPROM relating to the exemplary embodiment, and is a cross-sectionalview along segment B-B of FIG. 1;

FIG. 6C is a cross-sectional view showing the method of fabricating theEEPROM relating to the exemplary embodiment, and is a cross-sectionalview along segment C-C of FIG. 1;

FIG. 7A is a cross-sectional view showing the method of fabricating theEEPROM relating to the exemplary embodiment, and is a cross-sectionalview along segment A-A of FIG. 1;

FIG. 7B is a cross-sectional view showing the method of fabricating theEEPROM relating to the exemplary embodiment, and is a cross-sectionalview along segment B-B of FIG. 1;

FIG. 7C is a cross-sectional view showing the method of fabricating theEEPROM relating to the exemplary embodiment, and is a cross-sectionalview along segment C-C of FIG. 1;

FIG. 8A is a cross-sectional view showing the method of fabricating theEEPROM relating to the exemplary embodiment;

FIG. 8B is a cross-sectional view showing the method of fabricating theEEPROM relating to the exemplary embodiment;

FIG. 8C is a cross-sectional view showing the method of fabricating theEEPROM relating to the exemplary embodiment;

FIG. 9 is a cross-sectional view showing the method of fabricating theEEPROM relating to the exemplary embodiment;

FIG. 10 is a plan view showing the patterned shape of a polysilicon atthe lower portion of a polysilicon two-layer structure in the EEPROMrelating to the exemplary embodiment;

FIG. 11 is a drawing for explaining effects of the EEPROM relating tothe exemplary embodiment;

FIG. 12 is a plan view showing the patterned shape of a polysilicon atthe lower portion of a polysilicon two-layer structure in an EEPROMrelating to another exemplary embodiment;

FIG. 13 is a cross-sectional view showing the method of fabricating theEEPROM relating to another exemplary embodiment; and

FIG. 14 is a drawing for explaining effects of the EEPROM relating toanother exemplary embodiment.

DETAILED DESCRIPTION OF THE INVENTION First Exemplary Embodiment

An EEPROM, which is an exemplary embodiment of a nonvolatilesemiconductor memory of the present invention, will be describedhereinafter.

FIG. 1 is a plan view showing a portion of a memory cell array of anEEPROM relating to a first exemplary embodiment of the presentinvention. FIGS. 2 through 9 are cross-sectional views showing thefabricating method relating to the present invention, in the order ofthe processes thereof. Note that, in FIGS. 2 through 7, (A-A), (B-B),and (C-C) respectively show cross-sectional views along line A-A, lineB-B, and line C-C in FIG. 1. Namely, (A-A) and (B-B) are respectivelycross-sectional views in the bit line direction and the word linedirection at a memory cell. Further, (C-C) is a cross-sectional view ofplural word lines (word lines 10_1 through 10_3 which will be describedlater), and, in particular, shows the cross-section at the position of acontact portion of one of these word lines (word line 10_2 which will bedescribed later) and a metal wire of an upper portion.

FIGS. 8A through 9 are cross-sectional views along line C-C in FIG. 1.

(Overall Structure of EEPROM)

Referring to FIG. 1, plural word lines 10_1, 10_2, 10_3, 10_4, 10_5, . .. , and plural bit lines 20_1, . . . , are disposed at the EEPROM. TheEEPROM has a memory array 5 which is formed from memory cells which areprovided at the intersecting portions of these word lines and bit lines.For example, memory cell 2_21 is formed at the intersecting portion ofthe word line 10_2 and the bit line 20_1. The respective word lines 10_1through 10_5 are formed of polysilicon, and are connected to metal wires30_1 through 30_5 via contacts 12_1 through 12_5, respectively.

Note that, in the figures, the region where the memory array 5 is formedis denoted as cell area (CA), and the region where the contacts 12_1through 12_5 are formed is denoted as peripheral area (PA).

(Method of Fabricating EEPROM)

Next, a method of fabricating the EEPROM relating to the presentexemplary embodiment will be described in order with reference to FIG. 2through FIG. 8C.

First, a silicon oxide film of a film thickness of about 100 Å forexample is formed by thermally oxidizing the surface of a semiconductorsubstrate 50. Then, a silicon nitride film of a film thickness of about1000 Å for example is formed on the silicon oxide film by using a knownLPCVD (low pressure CVD) method. Then, the silicon oxide film and thesilicon nitride film are patterned by photolithography and etching. Bythermally oxidizing the surface of the semiconductor substrate 50 whichis exposed by this etching, an element isolating film 51 is selectivelyformed on the semiconductor substrate 50 as shown in (B-B) of FIG. 2. Anelement-forming region is demarcated by this element isolating film 51.

Note that the silicon oxide film and the silicon nitride film areremoved after the element isolating film 51 is formed.

Next, a silicon oxide film 52 (first insulating film) of a filmthickness of about 100 Å is formed on the surface of the element-formingregion under a dry oxidation condition of 900° C. for example. Then, apolysilicon 53 (first polysilicon film) of a film thickness of about 500Å for example is accumulated on the silicon oxide film 52 by LPCVD. Inthis way, a structure such as shown in FIG. 3 is formed.

Note that, thereafter, phosphorus (P) or arsenic (As) are introducedinto the polysilicon 53 in a concentration of 2E20 [1/cm³] by ioninjection or vapor phase diffusion.

Next, by photolithography, a region corresponding to the gate width of afloating gate is covered and the polysilicon 53 and the silicon oxidefilm 52 are anisotropically etched in that order. A tunnel oxide film(the silicon oxide film 52) and a floating gate (the polysilicon 53) arethereby patterned as shown in (B-B) of FIG. 4.

Note that, in this process, as shown in (C-C) of FIG. 4, the polysilicon53 is simultaneously patterned at the position of the word line 10_2where the contact portion with a metal wire of the upper portion isformed, i.e., at a substantially central position of the word line 10_2.The patterned shape (first shape) of the polysilicon 53 at this contactportion of the word line is, as will be described later, a shape whichincludes at least the contact portion of the word line and the metalwire of the upper layer.

Next, a silicon oxide film 54 (second insulating film) of a filmthickness of 100 Å is formed on the polysilicon 53 under a dry oxidationcondition of 950° C. for example. Then, a polysilicon 55 (conductivefilm) of a film thickness of 1000 Å for example is accumulated by LPCVDon the silicon oxide film 54. In this way, a structure such as shown inFIG. 5 is formed.

Note that, thereafter, phosphorus (P) or arsenic (As) are introducedinto the polysilicon 55 in a concentration of 4E20 [1/cm³] by ioninjection or vapor phase diffusion.

Next, for example, a tungsten silicide (WSix) film 56 is accumulated byCVD as a silicide film having a film thickness of about 1000 Å. Further,an NSG (Nondoped Silicate Glass) film 57 having a film thickness ofabout 1000 Å is accumulated by CVD. In this way, a structure such asshown in FIG. 6 is formed.

Subsequently, a predetermined region needed for the control gate iscovered by photolithography, and thereafter, by carrying out anisotropicetching, the gate of the memory cell is patterned as shown in (A-A) ofFIG. 7. At this time, as shown in (C-C) of FIG. 7, the word lines (thepolysilicon 55) are also patterned simultaneously.

Then, a mask oxide film having a film thickness of about 100 Å ispatterned and placed on the gate. Thereafter, phosphorus (P) or arsenic(As) is ion-injected at a dosage of about 1E15 [1/cm²], and diffusionlayers which become the source/drain regions are formed at both sides ofthe gate.

Next, the processes of forming the contacts of the word lines and themetal wires will be described with reference to FIGS. 8A through 8C andFIG. 9. FIGS. 8A through 8C and FIG. 9 show the formation processes inorder, with the state of the element shown in (C-C) of FIG. 7 being thestarting point. Note that, although not shown, in these processes,contact holes are simultaneously opened and metal wires are formed abovethe gate regions and the source/drain regions of the memory cells aswell.

First, a BPSG (Boro-Phospho Silicate Glass) film 58 serving as aninterlayer insulating film is accumulated (FIG. 8B) to a film thicknessof 1000 nm for example on the element which is formed as shown in FIG.8A (the same as (C-C) of FIG. 7). Then, a contact hole 58 a, at whichthe surface of a portion of the polysilicon 55 serving as a word line isexposed, is opened by using photolithography and anisotropic etching(FIG. 8C). RIE (Reactive Ion Etching) is used as this anisotropicetching, and, at this time, over-etching is carried out so that pooropening does not arise.

Next, as shown in FIG. 9, a conductor such as tungsten (W) or the likeis filled in the contact hole 58 a by sputtering or CVD. Then, byphotolithography and anisotropic etching, aluminum serving as the metalwires is patterned on the BPSG film 58, and a metal wire 302 serving asa word line is thereby formed.

(Structure of Contact Portion of Word Line and Metal Wire)

The structure of the contact portion of the word line and the metalwire, among the structures of the EEPROM which is formed by theabove-described fabricating method, will be described hereinafter withreference to FIG. 9 and FIG. 10.

By the above-described fabricating method, the polysilicon 53 is formedat the region beneath the polysilicon 55 which serves as the word line10_2, at the contact portion of the word line 10_2 and the metal wire30_2 in the EEPROM relating to the present exemplary embodiment as shownin FIG. 9. This two-layer structure of polysilicon is applied not onlyto the connected portion of the word line 10_2 and the metal wire 30_2,but also to, among the plural word lines, the word lines at which thesurface area of the patterned shape of the polysilicon 55 at the contactportion is relatively small (the word lines 10_2, 10_4 in the presentexemplary embodiment).

FIG. 10 is a drawing showing the patterned shape (first shape) of thelower polysilicon 53 (first polysilicon film), at the polysilicontwo-layer structure at the contact portion of the word line 10_2 and themetal wire 30_2 (see FIG. 1), and at the contact portion of the wordline 10_4 and a metal wire 30_4. In FIG. 10, these patterned shapes aredenoted as regions 100_2, 100_4.

As shown in FIG. 10, at the contact portion of the word line 10_2 andthe metal wire (30_2, see FIG. 1), the end portions of the region 100_2of the lower polysilicon 53 are formed so as to be separated fromcontact 12_2 by distance D1 at both sides in the bit line direction, andso as to be separated from the contact 12_2 by distance D2 at both sidesin the word line direction. Similarly, at the contact portion of theword line 10_4 and the metal wire (30_4, see FIG. 1), the end portionsof the region 100_4 of the lower polysilicon 53 are formed so as to beseparated from contact 12_4 by distance D1 at both sides in the bit linedirection, and so as to be separated from the contact 12_4 by distanceD2 at both sides in the word line direction.

Note that the patterning of the polysilicon 53 shown in FIG. 10 iscarried out simultaneously with the patterning of the floating gates ofthe memory cells as shown in FIG. 4, and therefore, no additionalprocess arises.

The effects of this structure of the contact portion will be describednext. FIG. 11 is a drawing for explaining the effects of the structureof the contact portion, and shows a case in which the etching at thetime of forming the contact is not carried out accurately above thepolysilicon 55.

Generally, in an EEPROM, in a case in which the interval betweenadjacent word lines (polysilicon) is narrow, it may be difficult to openthe contact hole 58 a with precision above the polysilicon 55. In theEEPROM relating to the present exemplary embodiment, in a case in whichthe contact hole 58 a cannot be opened accurately above the polysilicon55 and the position of opening thereof is offset to the front or back orto the left or right from the originally intended position, as shown inFIG. 11, the etching of the contact hole 58 a reaches the polysilicon 53and stops. Namely, among the polysilicon two-layer structure of thecontact portion of the word line and the metal wire, the selection ratioof the lower polysilicon 53 to the oxide film is about 50 times which ishigh, and therefore, the lower polysilicon 53 functions as an etchingstop layer. Accordingly, in the EEPROM relating to the present exemplaryembodiment, even in a case in which the contacts cannot be preciselyopened above the word lines, the electric signals from the peripheralcircuits are transferred reliably to the control gates via the wordlines.

Note that, generally, it is often the case that the minimum value of theinterval between the word lines (10_1 through 10_3) formed of thepolysilicon 55 is stipulated in the design rules from the standpoint ofthe accuracy of patterning. Accordingly, the EEPROM relating to theexemplary embodiment is particularly effective in cases in which theintervals between the adjacent word lines are narrow and the widths ofthe word lines (the polysilicon 55) cannot be made any greater.

Further, as shown in FIG. 10, at the contact portion, the polysilicon 53which serves as the etching stop layer is formed into a region at whichthe distance D1 is ensured in the bit line direction and the distance D2is ensured in the word line direction, with the contact being thesubstantial center. It is preferable that these distances D1, D2 bedetermined in accordance with the accuracy of the resist pattern of thephotolithography in the contact forming process. Namely, if thedistances D1, D2 are set to sizes of an extent that permit accuracy ofthe resist pattern at the time of contact formation, the lowerpolysilicon 53 always functions as an etching stop layer.

As described above, in accordance with the EEPROM of the presentexemplary embodiment, the polysilicon 53 (first polysilicon layer) of afixed region which is substantially centered around the contact hole isprovided at the contact portion of the word line and the metal wire.Therefore, even in cases in which the contact cannot be openedaccurately above the word line, the polysilicon 53 functions as anetching stop layer, and the substrate is not over-etched. Accordingly,even in cases in which the intervals between adjacent word lines arenarrow, in the EEPROM relating to the exemplary embodiment, problemscaused by poor junctions do not arise.

Note that, among the polysilicon two-layer structure of the contactportion of the word line and the metal wire which is described in thepresent exemplary embodiment, the material at the lower portion whichfunctions as the etching stop layer is not limited to polysilicon, andanother material can be used. It suffices for this material to have aselection ratio which is high with respect to the oxide film, and forthis material to function as an etching stop layer.

Further, the above-described polysilicon can be used as the material ofthe floating gate of the memory cell, and a material other thanpolysilicon can be used as the etching stop layer of the contact portionof the word line and the metal wire. For example, a metal material suchas tungsten silicide (WSix) or tungsten (W) or the like has a highetching selection ratio with respect to an oxide film, and therefore canbe used as the etching stop layer. However, in a case in which thematerial of the floating gate electrode of the memory cell and thematerial of the etching stop layer of the contact portion of the wordline and the metal wire are different, both cannot be patternedsimultaneously, and therefore, the number of processes increases.Accordingly, from the standpoint of laborsaving in the fabricatingprocesses, it is preferable that the etching stop layer be able to bepatterned simultaneously by the same material as the floating gate ofthe memory cell.

Second Exemplary Embodiment

An EEPROM, which is another exemplary embodiment of the nonvolatilesemiconductor memory of the present invention, will be describedhereinafter.

FIG. 12 is a plan view showing a patterned shape of the lowerpolysilicon 53 (first polysilicon film) in the polysilicon two-layerstructure in the EEPROM relating to the present exemplary embodiment. InFIG. 12, the patterned shape is shown as regions 100_1 through 100_5.

As shown in FIG. 12, in the EEPROM relating to the present exemplaryembodiment, differently than in the first exemplary embodiment, thepolysilicon 53 of a fixed region which is substantially centered aroundthe contact is formed at the contact portions of all of word lines (10_1through 10_5) and the metal wires, and not just at the contact portionsof some of the word lines. Namely, the two-layer structure ofpolysilicon, in which the polysilicon 53 is the first layer and thepolysilicon 55 is the second layer, is formed beneath the contacts 12_1through 12_5. The first polysilicon 53, which is the first layer, ispatterned into the regions 100_1 through 100_5 at which the respectivecontacts are the substantial centers thereof.

In the same way as in the first exemplary embodiment, the polysilicon 53which is patterned into the regions 100_1 through 100_5 functions as anetching stop layer.

Note that, in the same way as in the first exemplary embodiment, thepolysilicon 53 which is patterned into the regions 100_1 through 100_5is preferably formed simultaneously with the patterning of the floatinggate of the memory cell. Further, although the regions 100_1 through100_5 may be formed of a material other than the polysilicon 53, in thiscase, it is preferable that they be the same material as the floatinggate of the memory cell.

In the EEPROM relating to the present exemplary embodiment, thepolysilicon 53, which is for permitting positional offset of thecontacts, is patterned at all of the contact portions of the word linesand the metal wires. Therefore, the degrees of freedom in patterning theword lines (the polysilicon 55) are improved as compared with the firstexemplary embodiment. Accordingly, as shown in FIG. 12, all of the wordlines (10_1 through 10_5) can be formed rectilinearly.

Exemplary embodiments of the present invention have been described abovein detail, but the specific structures are not limited to theseexemplary embodiments, and changes in design, other modifications, andthe like within a scope which does not depart from the gist of thepresent invention also are included.

For example, in the above-described exemplary embodiments, a contacthole 58 a, at which the surface of a portion of the polysilicon 55serving as a word line is exposed, is opened by using photolithographyand anisotropic etching. However, as shown in FIG. 13, a contact hole 58a may be opened at the surface of a portion of the tungsten silicidefilm 56. Also in this modification, even when the etching at the time offorming the contact is not carried out accurately above the a tungstensilicide film 56 as shown in FIG. 14, the electric signals from theperipheral circuits are transferred reliably to the control gates viathe word lines.

Furthermore, for example, in the above-described exemplary embodiments,a thermal oxidation film is used as the tunnel oxide film. However, theformation conditions thereof may be other than those described above, oran insulating film such as a nitrided oxide film may be used. Moreover,in the above-described exemplary embodiments, the insulating film abovethe floating gate is formed by a single-layer oxide film, but may beformed by an ONO film, and with respect to the formation conditionsthereof as well, CVD may be used rather than thermal oxidation. Inaddition, aluminum is used at the metal wire layer in theabove-described exemplary embodiments, but a silicide such as WSi, or alayered film of polysilicon and silicide, may be used.

1. A method of fabricating a nonvolatile semiconductor memory having aplurality of word lines and a plurality of bit lines intersecting theword lines, and memory cells at intersecting portions of the word linesand the bit lines, the method comprising: providing a semiconductorsubstrate having a first insulating film thereon and a polysilicon filmon the first insulating film; patterning the polysilicon film to formfloating gates of the memory cells and an etching stop layer; forming asecond insulating film on the polysilicon film; forming a conductivefilm on the second insulating film; patterning the conductive film toform control gates of the memory cells and strip-shaped regions as theword lines, the word lines having a plurality of contact portionscovered and surrounded by the etching stop layer in a plan view;accumulating an interlayer insulating film on the conductive film; andetching the interlayer insulating film, and opening contact holes forthe contact portions above the conductive film.
 2. The method offabricating a nonvolatile semiconductor memory of claim 1, wherein theetching stop layer includes a plurality of rectangular regions, and eachrectangular region covers and surrounds a respective one of the contactportions, each side of the rectangular region being separated by apredetermined distance from the corresponding contact portion in theplan view.
 3. The method of fabricating a nonvolatile semiconductormemory of claim 1, wherein the polysilicon film has a thickness of 500Å.
 4. The method of fabricating a nonvolatile semiconductor memory ofclaim 1, further comprising forming the polysilicon film by low-pressurechemical vapor deposition (LPCVD).
 5. The method of fabricating anonvolatile semiconductor memory of claim 1, further comprisingintroducing phosphorus (P) or arsenic (As) into the polysilicon film ina concentration of 2E20 [1/cm³] by ion injection or vapor phasediffusion.
 6. The method of fabricating a nonvolatile semiconductormemory of claim 1, wherein the conductive film is a further polysiliconfilm having a thickness of 1000 Å.
 7. The method of fabricating anonvolatile semiconductor memory of claim 6, further comprising formingthe further polysilicon film by low-pressure chemical vapor deposition(LPCVD).
 8. The method of fabricating a nonvolatile semiconductor memoryof claim 6, further comprising introducing phosphorus (P) or arsenic(As) into the further polysilicon film in a concentration of 4E20[1/cm³] by ion injection or vapor phase diffusion.